Compiler Backend Engineer

Join Normal, a cutting-edge technology company focused on revolutionizing large-model inference. As a Compiler Backend Engineer, you will design and build custom compilation that maps LLM inference onto our unique hardware. You will work closely with the hardware and frontend compiler engineers, and your work will be measured against simulators, FPGA prototypes, and silicon. This is an exciting opportunity to work at the intersection of hardware and software, and to make a significant impact on the future of AI.

• Conception et développement de la compilation personnalisée qui mappe l'inférence LLM sur le matériel, de la planification à la génération de code.
• Responsabilité de la planification du travail et des données, de la fusion et des décisions de dispatch pour l'inférence LLM.
• Validation de chaque optimisation avec des résultats mesurés à partir de simulateurs, de prototypes FPGA, puis de silicium.

• Comfort working close to hardware: you think in terms of memory bandwidth and utilization as well as asymptotic complexity
• Deep experience with compiler optimization or code generation for accelerators or other non-CPU targets: scheduling, tiling, fusion, or resource allocation
• Track record of shipping optimizations that moved a measured performance number
• Comfort building software for hardware that is still evolving, from simulation through bring-up
• Willingness to design compilation approaches from first principles when existing ones don't fit the hardware
• Fluency in Python, and familiarity with C, C++, or Rust
• Experience with PyTorch's compilation stack (TorchDynamo, FX, Inductor, torch.export) or other ML compilers, such as IREE, TVM, or XLA
• Experience compiling for in-memory, spatial, or other non-von-Neumann compute targets
• Contributions to open-source compiler or kernel infrastructure (e.g., PyTorch, Triton, TVM, MLIR, LLVM)
• Background in hardware design tools such as logic synthesis or place-and-route
• Experience building or using cycle-level or performance simulators to guide optimization decisions
• Publishing or presenting compiler or performance work at venues such as MLSys, ASPLOS, or CGO