Design Verification Engineer
點序科技股份有限公司
Hsinchu, Taiwan Posted June 12, 2026
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Job Description
1.Integrated verification environment
2.Familiar with SoC level and IP level verification methodology
3.Develop verification plan and optimize verification flow
4.Familiar with verification methodology such as UVM, VMM, or OVM
- 職務類別：工程／研發／生技 / IC設計工程師
- 職務性質：全職
- 工作地點：新竹縣竹北市
- 工作時間：日班
- 工作經驗：2年以上
- 學歷要求：碩士
- 薪資：依學經歷、證照核薪(每月經常性薪資達4萬元以上)
- 需求人數：4
- 應徵截止：2026-12-31
資料來源：勞動部勞動力發展署「台灣就業通」（政府資料開放授權條款第1版）
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