Lead CPU Design Verification Engineer, Silicon

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits
Learn more about
benefits at Google
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Minimum qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog.
Experience with processor microarchitecture.

Preferred qualifications
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in low-power design verification.
Familiarity with ARM Instruction Set Architecture.
Knowledge of general purpose operating systems such as Linux and Android.

Responsibilities
Design verification for future CPU developments.
Build functional verification infrastructure, the infrastructure will include unit, multi-unit, core, and subsystem level verification environments.
Produce diagnostic code repositories that sufficiently enable production of quality CPU’s.
Verify and validate performance for both pre-silicon and post-silicon.