Physical Design Technical Leader

Cisco

San Jose, California, United States of America Posted October 24, 2026

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On-site Full-time Mid level
Job Description

We are looking for an ASIC Engineering Technical Leader to drive the verification and development of advanced optical transceivers and silicon photonics platforms. Lead RTL/netlist-to-GDSII implementation and collaborate with cross-functional teams. Ideal for candidates with significant ASIC/SoC physical design experience and expertise in high-speed CMOS nodes.

Required Skills
collaboration cross-functional collaboration
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