Senior Design Verification Engineer, Multimedia/AI/ML, Silicon

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and 's mission is to organize the world's information and make it universally accessible and useful.

Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $163000 - $236000 (USD) + 15% bonus target + equity + benefits Learn more about benefits at Google .

Minimum qualifications

• Bachelor's degree in electrical engineering or computer science, or equivalent practical experience.
• 8 years of experience with verification methodologies and languages (e.g., UVM and SystemVerilog).
• Experience with interconnect protocols (e.g., AXI, APB, ACE).
• Experience developing and maintaining verification testbenches, test cases, and test environments.

Preferred qualifications

• Master's degree or PhD in electrical engineering or computer science.
• Experience with low power, debug, GLS, formal verification.
• Experience in scripting languages (e.g., Python) for automation and analysis.
• Experienced in ARM or CPU based subsystem verification.
• Experience in cross-functional and global collaboration, fostering relationships and sharing insights to achieve company objectives.
• Experience leading design verification of IPs or subsystems delivered to many SoCs.

Responsibilities

• Work with designers, architects, and other stakeholders to come up with detailed test plans, dependencies, and deliverables, while representing DV status throughout the development process.
• Plan the verification of multimedia design blocks at subsystem level by understanding the design specification, and interacting with architecture and design engineers to identify important verification scenarios.
• Work with architecture, software, design, and back-end implementation stakeholders to make technical decisions.
• Create and enhance constrained-random verification environments using system verilog and UVM.
• Identify and implement improvements to the verification methodologies.
• Identify verification gaps and demonstrate advancement towards tape-out through comprehensive coverage metrics.
• Debug tests with design engineers to deliver functionally correct design blocks.