Senior SerDes Characterization Engineer, Platforms

Our platforms team designs and builds the hardware, software, and networking technologies that power all of Google's services. In this role, you will design and build the systems that are the heart of the computing infrastructure. You will develop from the lowest levels of circuit design to system design and see those systems all the way through to manufacturing. Your work has the potential to shape the machinery that goes into our data centers affecting Google users. As a member of the team, you will manage projects in multiple areas. You will also monitor the performance of vendors working on projects and evaluate new technologies.
The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits
Learn more about
benefits at Google
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Minimum qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
4 years of experience in high-speed electrical characterization, SerDes validation, or physical layer testing.
Experience with high-speed TX characterization and advanced test instrumentation (e.g., DCA, real-time scopes, spectrum analyzers).

Preferred qualifications
Master's or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field.
Experience with SerDes TX compliance testing and high-speed signal integrity principles.
Understanding of SerDes IO circuits, high-speed channel S-parameters, fixture de-embedding techniques, and transmission line theory.
Proficiency in Python, MATLAB, or C++ for automated instrument control (VISA, SCPI) and data extraction.
Strong collaboration skills with the ability to work independently in a fast-moving lab environment.

Responsibilities
Own transmitter (TX) and receiver characterization and compliance testing for Serializer/Deserializer (SerDes) interfaces across next generation compute and networking platforms.
Execute detailed TX physical layer metrics analysis, including Signal-to-Noise-and-Distortion Ratio, jitter decomposition, eye linearity, transition time, and pulse response measurements. Ensure test compliance against applicable IEEE 802.3, OIF-CEI, and proprietary high speed interconnect specifications.
Define and deploy automated test suites utilizing high performance real time and equivalent time (sampling/DCA) oscilloscopes, phase noise analyzers, and spectrum analyzers.
Partner with Physical Layer (PHY) design and signal integrity engineers to evaluate TX FIR filter presets, correlate silicon behavior against pre-silicon models, and optimize transmitter drive settings.
Develop robust data processing pipelines and visualization dashboards to report silicon health and parametric distributions.