Senior Manager of Digital Design

Join a hyper-growth company as a Senior Manager of Digital Design. You will lead the front-end digital design of high-performance PCIe & CXL, UAL, and ethernet devices that enable reliable connectivity in rack-scale AI infrastructure. You will guide projects from requirements and architecture through RTL development, verification, physical design, tape-out, and product shipment. This is an opportunity to influence the development of purpose-built connectivity products and help deliver silicon that advances the next generation of AI systems.

• Lead the front-end digital design of high-performance PCIe & CXL, UAL, ethernet devices, guiding projects from requirements through product shipment.
• Drive the delivery of complex devices, maintaining clear milestones, technical decisions, risk tracking, and schedule accountability.
• Lead, mentor, and develop a team of digital design engineers, fostering technical excellence, accountability, and effective collaboration.

• Experience with PCIe & CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations
• Demonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices of reasonable complexity
• Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations
• Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality
• 3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field
• Expertise in RTL quality methodologies, design reviews, lint, clock-domain and reset-domain considerations, synthesis, timing, and signoff readiness
• Experience defining or improving design checklists, development flows, quality gates, and cross-functional tape-out processes
• Track record of balancing performance, power, area, schedule, and risk across large SoC or ASIC programs
• Building design blocks with large physical floorplan sizes is a plus
• Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field