Technical Lead Engineer (Design Verification)

Join Astera Labs as a Technical Lead Engineer in Design Verification. In this role, you will define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will collaborate closely with various teams, lead verification planning and execution, develop and enhance testbenches, and drive functional and code coverage analysis. This position offers flexible time off, parental leave, a 401K plan, and competitive medical, dental, and vision plans.

• Definir y entregar una verificación robusta para silicio de conectividad de próxima generación.
• Desarrollar planes de verificación a nivel de bloque y subsistema a partir de especificaciones, arquitectura y requisitos de diseño.
• Construir y mejorar bancos de pruebas reutilizables basados en UVM y SystemVerilog, y crear escenarios de prueba.

• Hands-on experience with SystemVerilog and UVM-based verification environments
• 5–8 years of experience in design verification for complex ASICs or SoCs
• Strong technical leadership, debugging, communication, and collaboration skills in a fast-paced product development environment
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field
• Familiarity with simulation, waveform-debug, regression, and coverage tools
• Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models
• Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• Knowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologies
• Experience with Python, PowerShell, or Tcl for verification automation and regression infrastructure
• Experience verifying PCIe, UALink, UCIe, or other high-speed connectivity and switching protocols
• Understanding of AI or data-center system architectures, including accelerator, memory, and fabric connectivity