Hardware Engineer (Physical Design)

Join Normal as a Physical Design Engineer, where you will be responsible for the end-to-end silicon realization path, from synthesis and physical floorplanning to timing signoff and GDSII tapeout. You will work closely with RTL and architecture teams to shape physical feasibility early in the design cycle and drive the full backend implementation flow. The ideal candidate will have a strong background in physical design, experience with industry-standard tools, and a track record of successful tapeouts.

• Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis (CTS), and place-and-route (P&R).
• Own static timing analysis (STA), timing constraints creation/validation, and signoff timing closure across all operating corners and modes.
• Execute full chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, ensuring seamless handoff to the foundry.

• We are looking for a seasoned engineer who thrives in cross-functional environments and takes pride in tapeout-proven execution
• The ideal candidate brings a meticulous approach to physical signoff, maintains clarity in fast-paced build cycles, and is excited to solve the physical constraints of novel computing architectures
• Backend Debugging Instincts: Strong problem-solving skills in analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations
• PD Flow Expertise: Deep hands-on experience with industry-standard physical design tools (e.g., Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, Calibre) across floorplanning, P&R, CTS, and signoff timing closure
• Tapeout Track Record: At least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes
• Cross-Functional Feasibility: Ability to collaborate effectively with RTL, architecture, and DFT teams to influence floorplanning, pin placement, and early physical feasibility
• Experience at an AI or high-performance compute (HPC) chip startup where design, verification, and PD work in tight iteration cycles
• Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (e.g., chiplets, 2.5D/3D integration)
• Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows