Senior ASIC Physical Design Engineer

Join Tensordyne, a leader in generative AI inference acceleration products. As a Senior ASIC Physical Design Engineer, you will lead the front-end physical design and engineering workflow development for our multimodal AI products. You will work closely with your ASIC team members to improve their workflows and EDA needs, and drive the optimization and exploration of new physical design workflows and technologies. This is a hands-on role ideal for ASIC physical design experts with a passion for generative AI and complex technical challenges.

• Lead ASIC front-end physical design and associated engineering workflow development for multimodal generative AI inference acceleration products.
• Drive optimization, implementation, and exploration of new frontend physical design workflows and technologies for the full ASIC chip design process.
• Collaborate closely with ASIC team members engaged in the design and verification of products to understand and improve their workflows and EDA needs.

• Excellent analytical, written, and verbal interpersonal skills along with an ability to productively collaborate within a global engineering team that moves at a startup pace
• Understanding of STA analysis and constraints for block level and knowledge of full chip timing analysis
• Strong physical design knowledge for front-end optimization using standard EDA tools
• Bachelor’s or Master's degree in Computer Science, Computer Engineering, Electrical Engineering or a related technical field
• Experience leading and supporting backend design team with understanding of clock trees, routing , DRC, LVS, metal fill till artwork release
• 10+ years of hands-on ASIC engineering experience, that includes deep knowledge of VLSI/SoC chip physical design workflows, with EDA tools like Cadence/Synopsys (Genus/DC), power analysis, clock methodology, and other commonly used aspects of physical design flows